In electronic devices and systems that use a large number of slope (ramp) analog to digital converters (ADCs) on a single chip, or die, power consumption by comparators associated with the analog to digital converters can be significant. FIG. 1 illustrates a typical imaging array 10 with a single ADC per column. For operation of the imaging array, a row of pixels is selected and an appropriate voltage on each column is sampled by the sample and hold units 15-1 . . . 15-M. A ramp generator 20 is started. Each column has a comparator 25-1 . . . 25-M that toggles when its sampled voltage is equal to the voltage of ramp generator 20. Such an architecture uses a large number of sample and hold units and comparators. For example, in CMOS imaging applications, a million pixel device is not uncommon. In a typical architecture, a million pixel device could require 1000 comparators for a 1000×1000 pixel topology. Such a large number of comparators places two conflicting design constraints on the comparator design: low power operation and high speed operation. In addition to low power consumption, high speed operation is desired since each comparator must switch within one clock cycle of a digital ramp generator clock. If the comparator switches too late, the incorrect value of the ramp generator will be latched, which will resemble an unwanted offset.